Semiconductor devices typically contain interconnects, such as vias and contacts, which connect conductive elements in non-successive layers within a semiconductor device. A via generally connects two metallic elements in different layers of a semiconductor device. A contact generally connects metallic and non-metallic conducting or semiconducting (such as silicon, polysilicon, or silicide) elements in different layers of a semiconductor device. As used herein, a “conductive” element or layer is defined to include both conducting and semiconducting elements or layers. The interconnect is typically formed in an inter-level dielectric (“ILD”) layer disposed between the layers to be connected. A common dielectric material used for the ILD is silicon dioxide, but more recently organic materials providing lower dielectric constants, such as SiLK (silicon low-k) semiconductor dielectric resins, available from The Dow Chemical Company, and other polymers and cross linked polyarylene ether polymers, have been used or proposed for the ILD.
Generally, the ILD is formed on one of the conductive layers to be connected, and a hole or trench is etched into the ILD using, for example, plasma etching or reactive ion etching. The lower conductive layer forms the bottom of the hole. A liner may be formed in the hole, for example using physical vapor deposition, by coating the walls and floor of the hole with a diffusion barrier material, such as tungsten nitride, tantalum nitride, titanium nitride, or titanium tungsten. A plug is generally formed by depositing (e.g., using chemical vapor deposition or electroplating) conductive material (e.g., tungsten or copper) in the hole. The surface of the wafer may be planarized, for example with chemical mechanical polishing, and then the second layer to be connected is formed on the ILD. This layer is typically a metal layer, such as an aluminum alloy (e.g., aluminum copper) or copper, although it may be composed of other conductive materials.
After the hole is etched, but before the liner or plug are formed, the hole is typically cleaned (also referred to as “pre-cleaning”) to remove any oxide from the surface of the lower conductive layer, as well as any other residue left from the etch chemistry used to form the hole. The cleaning may be performed with a wet etch technique, but it is generally preferable to use a dry etch process such as radio frequency (“RF”) sputtering with, for example, an argon plasma, to physically etch the surface oxide. The sputter clean process of the prior art, however, may itself cause problems with the interconnect, in particular when an organic ILD is used. One disadvantage of the prior art is that organic ILD material may be dislodged from the sidewalls of the hole when plasma ions collide with the sidewalls, and then may deposit on and contaminate the lower conductive layer and increase contact resistance. Another disadvantage of the prior art is that the re-deposited organic byproduct may degrade the adhesion of the liner or plug to the underlying conductive layer. In addition, the redeposited organic material may cause interconnect reliability problems, such as interconnect resistance shift during thermal stress.